FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach

In this paper we propose an area-time efficient architecture for the realization of self-clocked MAC filters on FPGA. First, the self-timed 4-phase oscillator/counter is analyzed and characterized, showing experimental results in comparison with simulation foreseen. Next, the proposed filter architecture, based on circular memories, is described and efficiently implemented as an IP module using device primitives and relative location constraints. Finally, an example using the proposed architecture is implemented on an FPGA and compared with a standard IP filter of similar characteristics, pointing out the advantages of our approach.