Title :
Performance and energy analysis of task-level graph transformation techniques for dynamically reconfigurable architectures
Author :
Noguera, Juanjo ; Badia, Rosa M.
Author_Institution :
InkJet Commercial Div., Hewlett-Packard, Barcelona, Spain
Abstract :
In this paper, we present an analysis of the impact in both performance and energy of several task-level graph transformation techniques to exploit the parallel processing capabilities of run-time partially reconfigurable architectures. The proposed techniques have been applied to an image processing application (i.e., image sharpening), which has been implemented in a real research platform.
Keywords :
graph grammars; parallel processing; programmable logic devices; reconfigurable architectures; energy analysis; image processing; parallel processing; reconfigurable architectures; task-level graph transformation; Computer architecture; Dynamic scheduling; Embedded system; Energy consumption; Image processing; Parallel processing; Performance analysis; Random access memory; Reconfigurable architectures; Runtime;
Conference_Titel :
Field Programmable Logic and Applications, 2005. International Conference on
Print_ISBN :
0-7803-9362-7
DOI :
10.1109/FPL.2005.1515786
