• DocumentCode
    2140527
  • Title

    FPGA implementation of a GF(22M) multiplier for use in pairing based cryptosystems

  • Author

    Keller, Maurice ; Kerins, Tim ; Marnane, William

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Ireland
  • fYear
    2005
  • fDate
    24-26 Aug. 2005
  • Firstpage
    594
  • Lastpage
    597
  • Abstract
    In this paper an architecture for GF(24m) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.
  • Keywords
    cryptography; logic design; multiplying circuits; FPGA implementation; GF(22M) multiplier; Tate pairing; hardware accelerator; pairing based cryptosystems; Arithmetic; Clocks; Costs; Elliptic curve cryptography; Elliptic curves; Equations; Field programmable gate arrays; Galois fields; Hamming weight; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2005. International Conference on
  • Print_ISBN
    0-7803-9362-7
  • Type

    conf

  • DOI
    10.1109/FPL.2005.1515793
  • Filename
    1515793
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2140527