DocumentCode :
2140542
Title :
Emulating output queueing with the Central-stage Buffered Clos packet switching network
Author :
Ma, Xiangjie ; Lan, Julong ; Zhang, Baisheng
Author_Institution :
Inf. Eng. Inst., Inf. Eng. Univ., Zhengzhou
fYear :
2008
fDate :
15-17 May 2008
Firstpage :
98
Lastpage :
103
Abstract :
Clos packet switching networks are the next step in scaling current Crossbar switches to large number of ports. The novel central-stage buffered Clos-network (CBC network) has the merit of fully memory-sharing among all inputs and outputs and was proved to emulate an FCFS-OQ switch with the central module count (i.e. m) about four times of the input modules count (i.e. n). This leads to high hardware complexity when designing a CBC network with high radices. This paper studies the graphic model of the CBC network, proposes analytical methods including the stable path set and the stable vertex pair set, and demonstrates that the CBC network can match an FCFS-OQ switch with the central module count m>=n. By comparison, the number of the central modules in our result is only a quarter of that in previous results, and therefore the implementation of a CBC network become much simpler in practical routers.
Keywords :
multistage interconnection networks; network routing; packet switching; queueing theory; CBC network; FCFS-OQ switch; central-stage buffered clos packet switching network; crossbar switches; graphic model; memory-sharing network; output queueing emulation; stable path set method; stable vertex pair set method; Cyclic redundancy check; Fabrics; Graphics; Hardware; Mathematical model; Packet switching; Scheduling algorithm; Switches; Telecommunication traffic; Traffic control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Switching and Routing, 2008. HSPR 2008. International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-1981-4
Electronic_ISBN :
978-1-4244-1982-1
Type :
conf
DOI :
10.1109/HSPR.2008.4734428
Filename :
4734428
Link To Document :
بازگشت