Implementation of ranking filters on general purpose and reconfigurable architecture based on high density FPGA devices

In this paper we present the implementation of ranking filters on two different computer architectures. First we consider a general purpose computer based on Intel Pentium 4 microprocessor and we show that when SSE2 extension is used the throughput vary from 20 to 200 MB/sec, depending on the neighborhood size and rank value. Secondly, we consider a reconfigurable architecture using hundreds of processing elements running bit-serial algorithms and implemented in a high density FPGA device. The throughput of such system varies from 900 to 2600MB/sec which is 13 to 40 times faster than the considered general purpose architecture.