DocumentCode :
2140621
Title :
Applying quantum search to automated test pattern generation for VLSI circuits
Author :
Singh, Sarbjeet ; Singh, MR Amardeep
Author_Institution :
Dept. of Comput. Sci & Eng., Thapar Inst. of Eng. & Technol., Punjab, India
fYear :
2003
fDate :
27-29 Aug. 2003
Firstpage :
648
Lastpage :
651
Abstract :
We present a quantum search algorithm for automated test pattern generation (ATPG) of combinatorial VLSI circuits. This problem can be viewed as an optimization problem because digital circuits can be modeled as a neural network and the problem become to minimize the energy function of this neural network. The solution of the equation gives us the test vector. Here specific aspects of quantum theory like superposition and quantum parallelism are applied to this problem. In quantum search algorithm this problem is viewed as a searching problem where the search function (also called oracle) f(x)=1 if the value of the energy function of the neural network is 0 otherwise f(x)=0. Quantum mechanics help us to search a group of items simultaneously from the search space rather than one item at a time. The algorithm is so efficient that it requires only, on average, roughly √N (where N is the total number of vectors) searches to find the desired test vector, as opposed to a search in classical computing, which on average needs N/2 searches. A comparison is made between exhaustive, simulated annealing and quantum based search techniques. Experimental results show that the quantum search algorithms are more efficient than classical algorithms and can be applied with more efficiency on a quantum computer.
Keywords :
VLSI; automatic test pattern generation; computational complexity; neural nets; quantum computing; quantum theory; simulated annealing; system-on-chip; ATPG; VLSI circuit; automated test pattern generation; neural network; optimization problem; quantum computer; quantum mechanics; quantum parallelism; quantum search algorithm; quantum theory; simulated annealing; superposition; Automatic test pattern generation; Circuit testing; Digital circuits; Equations; Neural networks; Parallel processing; Quantum computing; Quantum mechanics; Test pattern generators; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Computing, Applications and Technologies, 2003. PDCAT'2003. Proceedings of the Fourth International Conference on
Print_ISBN :
0-7803-7840-7
Type :
conf
DOI :
10.1109/PDCAT.2003.1236383
Filename :
1236383
Link To Document :
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