Fabrication and electrical characterization of 3D vertical interconnects

3D die-stacking (Tanida et al, 2003; Hara et al, 2005) and wafer-stacking (Morrow et al, 2004) integration have recently been demonstrated using copper (Cu) interconnections and through silicon via technology. In 3D die-stacking approach, the Cu vertical interconnections are fabricated on the front-side of the silicon wafer along with the active circuitry followed by wafer thinning and die-stacking. The limitation of this approach is the impact to active circuitry from vertical interconnects processing. With the 3D wafer stacking approach, the wafers are bonded with the prefabricated active circuitry face-to-face prior to wafer thinning and Cu interconnects fabrication and inherently limit stack die configuration to matched die sizes. This approach has inherent benefits and limitations depend to a large extent on the targeted applications. In this paper, we present an alternate 3D die-stacking approach which involves wafer thinning prior to Cu interconnect fabrication in a silicon wafer consisting of pre-fabricated active circuitry. This approach allows for mixed die size and technology node integration in multi-chip packages while maximizing known good die yields. In this approach the electrical connection to the active circuitry is made through the Cu plated through-silicon via to large arrays of tungsten (W) contacts at the bulk silicon interface. The challenges in through-silicon via processing using this 3D die-stacking approach will be discussed. Backside processing impact to pre-fabricated transistors and fundamental RC performance of the through silicon via landing on contact will be presented