DocumentCode :
2140725
Title :
Mapping data-flow graph to loop engine on array processor
Author :
Dou, Yong ; Lu, Xicheng
Author_Institution :
Nat. Lab. for Parallel & Distributed Process., Hunan, China
fYear :
2003
fDate :
27-29 Aug. 2003
Firstpage :
676
Lastpage :
680
Abstract :
We present a novel architecture for array processor, called LEAP, which is a set of simple processing elements. The targeted programs are perfect innermost loops. By using the technique called if-conversion, the control dependence can be converted to data dependence to prediction variables. Then an innermost loop can be represented by a data dependence graph, where the vertex supports the expression statements of high level languages. By mapping the data dependence graph to fixed PEs, each PE steps the loop iteration automatically and independently at the runtime. The execution forms multiple pipelining chains. The simulation of four loops of LFK shows the effectiveness of the LEAP architecture, compared with traditional CISC and RISC architectures.
Keywords :
data flow graphs; multiprocessing systems; parallel architectures; parallel programming; pipeline processing; program control structures; reduced instruction set computing; CISC architecture; LEAP architecture; RISC architecture; array processor; chip multiprocessor; control dependence; data dependence; data-flow graph; if-conversion technique; loop engine; multiple pipeline chaining; Automatic control; Computer architecture; Distributed processing; Engines; Laboratories; Pipeline processing; Process design; Routing; Runtime; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Computing, Applications and Technologies, 2003. PDCAT'2003. Proceedings of the Fourth International Conference on
Print_ISBN :
0-7803-7840-7
Type :
conf
DOI :
10.1109/PDCAT.2003.1236389
Filename :
1236389
Link To Document :
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