Performance improvements using coarse-grain reconfigurable logic in embedded SOCs

A hardware/software partitioning methodology for improving applications´ performance in embedded single-chip systems is presented. Critical software parts are accelerated on hardware of a system comprised by an embedded processor and coarse-grain reconfigurable hardware. The reconfigurable hardware is realized by a 2-dimensional array of processing elements. The partitioning method uses a basic-block level analysis procedure for detecting kernels in software. A mapping algorithm for coarse-grain reconfigurable arrays has been developed for estimating the execution time of kernels on the reconfigurable hardware. The proposed partitioning flow has been largely automated for a program description in C language. Analytical hardware/software experiments on five real-world applications are given. The results show that by mapping critical parts on coarse-grain reconfigurable hardware, speedups ranging from 1.2 to 3.7, with an average value of 2.3, are achieved.