Title :
Influence of transistor degradation on CMOS performance and impact on life time criterion
Author :
Winnerl, J. ; Lill, A. ; Schmitt-Landsiedel, D. ; Orlowski, M. ; Neppl, F.
Author_Institution :
Siemens AG, Munich, West Germany
Abstract :
For more realistic lifetime predictions of CMOS technology a stress test was developed that yields the relevant transistor degradation under dynamic stress and simultaneously the impact of transistor degradation on circuit speed performance. Thus uncertainties with respect to duty factor estimations and special dynamic effects are eliminated. The influence on circuit performance can be directly characterized by the change of ring oscillator frequency. The relative frequency change was found to be about one order of magnitude similar than the transconductance change. Based on these results, a less restrictive criterion is introduced. If 1-2% frequency change is allowed the acceptable Delta g/sub m//g/sub m/ (where g/sub m/ is the extrinsic transconductance) can be increased from the typical value of 10% to 25%, resulting in an considerably increased lifetime. For a given lifetime this can be utilized to reduce the gate length from 1 mu m to 0.4 mu m without reducing the supply voltage, extending the use of 5-V supply voltage into the deep sub- mu m regime.<>
Keywords :
CMOS integrated circuits; hot carriers; integrated circuit testing; life testing; CMOS technology; circuit speed performance; dynamic stress; extrinsic transconductance; gate length; life time criterion; relative frequency change; ring oscillator frequency; stress test; transconductance change; transistor degradation; CMOS technology; Circuit optimization; Circuit testing; Degradation; Frequency; Life testing; Stress; Transconductance; Uncertainty; Voltage;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32791