• DocumentCode
    2141072
  • Title

    Control and management plane in a multi-stage software router architecture

  • Author

    Bianco, A. ; Birke, R. ; Finochietto, J. ; Giraudo, L. ; Marenco, F. ; Mellia, M. ; Khan, A. ; Manjunath, D.

  • Author_Institution
    Dip. di Elettron., Politec. di Torino, Turin
  • fYear
    2008
  • fDate
    15-17 May 2008
  • Firstpage
    235
  • Lastpage
    240
  • Abstract
    Software routers based on personal computer (PC) architectures are receiving increasing attention in the research community. However, a router based on a single PC suffers from limited bus and central processing unit (CPU) bandwidth, high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multi-stage architectures created by interconnecting several PCs are an interesting alternative since they allow to i) increase the performance of single-software routers, ii) scale router size, iii) distribute packet-forwarding and control functionalities, iv) recover from single-component failures, and v) incrementally upgrade router performance. However, a crucial issue is to hide the internal details of the interconnected architecture so that the architecture behaves externally as a single router, especially when considering the control and the management plane. In this paper, we describe a control protocol for a previously proposed multi-stage architecture based on PC interconnection. The protocol permits information exchange among internal PCs to support: i) configuration of the interconnected architecture, ii) packet forwarding, iii) routing table distribution, iv) management of the internal devices. The protocol is operating system independent, since it interacts with software routing suites such as Quagga and Xorp, and it is under test in our labs on a small-scale prototype of the multi-stage router.
  • Keywords
    computer architecture; computer network management; operating systems (computers); public domain software; routing protocols; PC interconnection; Quagga; Xorp; central processing unit bandwidth; control plane; control protocol; high memory access latency; information exchange; interconnected architecture configuration; internal device management; limited scalability; management plane; multistage software router architecture; network interface cards; packet forwarding; personal computer architectures; resilience mechanisms; router size scaling; routing table distribution; single-component failure recovery; single-software routers; Bandwidth; Central Processing Unit; Computer architecture; Delay; Microcomputers; Network interfaces; Personal communication networks; Resilience; Routing protocols; Scalability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Switching and Routing, 2008. HSPR 2008. International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-1981-4
  • Electronic_ISBN
    978-1-4244-1982-1
  • Type

    conf

  • DOI
    10.1109/HSPR.2008.4734449
  • Filename
    4734449