Title :
Analysis and Improvement of Dynamic Multi-core Hardware Prefetch Technology Based on Pre-execution
Author :
Fang, Juan ; Zhang, Hongbo
Author_Institution :
Coll. of Comput. Sci., Beijing Univ. of Technol., Beijing, China
Abstract :
Multi-core processor has been widely used for lower power consumption and high performance, but it also aggravates the “Memory Wall” problem, the increasing memory access latency limits the further improvement of multi-core´s performance. Therefore, prefetching technology is an effective way to address this problem. This paper analyses the dynamic multi-core hardware prefetching technology based on pre-execution and brings up some improvements, besides, it raises the challenges of prefetching techniques for multi-core and the likely solution to the challenges.
Keywords :
memory architecture; multiprocessing systems; storage management; memory access latency; memory wall problem; multicore processor; pre-execution technology; prefetching technology; Hardware; Iron; Multicore processing; Pipelines; Prefetching; CMP; coherency of cache; multi-core prefetch; multicore architecture; pre-execution based prefetching;
Conference_Titel :
Frontier of Computer Science and Technology (FCST), 2010 Fifth International Conference on
Conference_Location :
Changchun, Jilin Province
Print_ISBN :
978-1-4244-7779-1
DOI :
10.1109/FCST.2010.33
