FPGA interconnect fault tolerance

The area occupied by wiring channels in an FPGA die is significant, occupying up to 10 metal layers for the latest manufacturing technology. With current trends aiming to reduce the area occupied by wiring segments in the routing channels, wire width and wire spacing have been reduced. This has in turn led to higher occurrences of wiring defects, such as breaks and shorts, and losses in manufacturing yield and fewer functioning devices at fixed manufacturing costs. In the context of fault tolerance, an integral part of any scheme is fault detection and diagnosis. A device is first tested in order to find out whether a fault is present; faulty chips then undergo further tests in order to locate the fault and discover its location and nature. In order not to affect performance and user loads, the testing procedures have to be efficient and compact. This has brought the development of fast testing procedures to complement different fault tolerance schemes. An earlier paper (Campregher et al., 2004) presented a built-in self-test (BIST) method that can efficiently identify the exact location of the interconnect fault. The method is based on a concept known as fault grading which utilizes defect knowledge during manufacturing test to classify faulty devices into different defect groups. Currently, work is proceeding to improve the yield prediction models and assumptions. The main objective of this work is to generate a framework to compare different fault tolerance schemes and analyze their benefits from a manufacturing yield perspective.