Low dissipation nanoscale transistor physics and operations

Power dissipation has recently overtaken performance as the most important challenge in scaling nanoscale transistors. In this paper, we have proposed and preliminarily analyzed novel device concepts to reduce both the off-state leakage dissipation as well as the dynamic power consumption. The off-state leakage can be selectively suppressed using a wide bandgap drain heterojunction architecture. On the other hand, the dynamic power can be reduced using an asymmetric gate biasing scheme. We have also discussed the enabling device physics and operating principles.