CMOS gate height scaling

The work addresses benefits and performance impacts resulted from CMOS gate height reduction. The experiment shows that capacitance arising between the CMOS source/drain contact and the gate electrode decreases about linearly as the gate height scales down. The result also shows that stress liner techniques continue providing strong performance enhancement for CMOS as the gate height scales from 100 nm to 50 nm. For ring oscillators built with 45 nm node CMOS technology, the capacitance benefit associated with gate height reduction from 100 nm to 80 nm improves the circuit speed by ~3%.