Title :
Viterbi hardware implementation for GSM
Author :
Wang Kaiming ; Wu Weiling
Author_Institution :
Dept. of Inf., Beijing Univ. of Posts & Telecommun., China
Abstract :
The paper presents a novel Viterbi decoder hardware implementation, with the code rate R=1/2 and the constraint length K=5, for the GSM land mobile system. With the use of one XILINX FPGA 3090 chip to replace the ACSs´ function, which results in a much simpler hardware and routing structure, this system makes the final ASIC fabrication a very direct consequence.<>
Keywords :
application specific integrated circuits; block codes; cellular radio; codecs; convolutional codes; decoding; digital signal processing chips; logic arrays; maximum likelihood estimation; ASIC fabrication; GSM land mobile system; Viterbi decoder hardware implementation; XILINX FPGA 3090 chip; code rate; constraint length; routing structure; Application specific integrated circuits; Convolutional codes; Decoding; Electronics packaging; Fabrication; Field programmable gate arrays; GSM; Hardware; Routing; Viterbi algorithm;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.327937
