Next generation architectures and CAD for power aware programmable fabrics

As fabrication technology continues to scale, several million transistors are being integrated in modern reconfigurable architectures like FPGAs. This has made such architectures a viable platform for system implementation. However, the luxury of system implementation along with the flexibility to reprogram comes at the cost of substantial hardware overhead that has made such fabrics extremely power hungry. In current nanometer designs, static or leakage power has emerged as a dominant component in total power consumption. In order to evolve under aggressive technology scaling, modern reconfigurable architectures must incorporate power, especially static power as an important design variable along with performance, density etc. Our present research work explores power aware reconfigurable architectures along with new design methodology which exploits novel architectural features for power savings.