Title :
Stress engineering for 32nm CMOS technology node
Author :
Wu, Jeff ; Wang, Xin
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Various aspects of the influence of scaling on stress engineering for 32 nm node are reviewed. Numerical simulations of width effect of embedded SiGe (e-SiGe) induced stress and the physical mechanism of stress memorization technique (SMT) are presented in this paper. A novel SMT scheme to further improve performance of PMOSFET is reviewed and demonstrated using numerical simulations.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; scaling circuits; CMOS technology node; PMOSFET; SiGe; embedded induced stress; numerical simulations; scaling influence; size 32 nm; stress engineering; stress memorization technique; Boundary conditions; CMOS technology; Compressive stress; Instruments; MOSFET circuits; Numerical models; Numerical simulation; Piezoresistance; Surface-mount technology; Tensile stress;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734486
