Dopant-segregated source/drain technology for high-performance CMOS

Schottky barrier MOSFETs (SBTs) have attracted much attention as a candidate for achieving high-performance in future ULSIs. Their potential advantages are low electrode resistance, short channel effect immunity and high carrier injection velocity, and many more. The major obstacle is however, to reduce the Schottky barrier height (ÿ_b) in these devices (both n- and pMOSFETs) since large ÿ_b severely limits the current drivability. One promising candidate to achieve the low ÿ_b, is dopant-segregated Schottky (DSS) junctions. In this paper, we report process and characteristics of DSS junctions.