DocumentCode :
2142248
Title :
Ternary Schmitt circuit based on neuron-MOS transistor
Author :
Guoqiang Hang ; Danyan Zhang ; Xiaohui Hu ; Yang Yang ; Xiaohu You
Author_Institution :
Sch. of Inf. & Electr. Eng., Zhejiang Univ. City Coll., Hangzhou, China
fYear :
2013
fDate :
23-25 July 2013
Firstpage :
1748
Lastpage :
1752
Abstract :
A novel voltage-mode CMOS ternary Schmitt trigger using neuron-MOS transistors is presented. By controlling the voltages of the multiple-input gates, the neuron-MOS literal circuits with hysteresis characteristics are firstly designed. Then, the transmission switches used to pass ternary signal are controlled by the outputs of the literal circuits to realize two hysteresis loops of ternary Schmitt circuit. The benefit of the proposed ternary Schmitt trigger is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer, instead of the multi-level ion implantation applied in the conventional voltage-mode multiple-valued circuits. The two hysteresis loops are fully adjustable by sizing the ratio of capacitive coupling coefficients. Besides, as the variable threshold voltage can be achieved easily in neuron-MOS literal circuits, the proposed ternary Schmitt trigger has a simple structure. The effectiveness of the proposed ternary Schmitt trigger has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology, and the discrepancy of hysteresis values between the simulated and theoretical results is smaller than 6%.
Keywords :
CMOS logic circuits; MOSFET; multivalued logic circuits; trigger circuits; 2-ploy layer; HSPICE simulation; capacitive coupling coefficients; hysteresis loops; multilevel ion implantation; neuron-MOS literal circuits; neuron-MOS transistors; size 0.35 mum; voltage-mode CMOS ternary Schmitt trigger; voltage-mode multiple-valued circuits; CMOS integrated circuits; Hysteresis; Inverters; Logic gates; Switches; Threshold voltage; Transistors; CMOS circuits; Schmitt trigger; floating-gate MOS transistor; multiple-valued logic; neuron-MOS transistor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Natural Computation (ICNC), 2013 Ninth International Conference on
Conference_Location :
Shenyang
Type :
conf
DOI :
10.1109/ICNC.2013.6818265
Filename :
6818265
Link To Document :
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