Low complexity equalization for cable modems

Cable modems are a relatively recent development in the Internet access business in which the residential user has a high speed link to his home over the coaxial cable plant. In previous cable modem designs the equalizer, an adaptive filter that compensates for distortion in the coaxial cable, dominates the chip area, at about 50%. A significant reduction in equalizer size will therefore reduce the cost and complexity of the overall chip significantly. In this paper we describe a design that takes advantage of the relatively low sample rate of the cable modem equalizer to reduce the complexity of the equalizer. We show that a length 12 complex equalizer with full LMS update can be implemented with only four multipliers using an 80 MHz clock. For the decision feedback equalizer we implement a minimum gate width 12 by 4 multiplier using 0.35 μm technology. This design demonstrates a way of reducing circuit complexity