DocumentCode
2142562
Title
A Formal Approach to Verify Mapping Relation in a Software Product Line
Author
Satyananda, Tonny Kurniadi ; Lee, Danhyung ; Kang, Sungwon
Author_Institution
Inf. & Commun. Univ., Daejeon
fYear
2007
fDate
16-19 Oct. 2007
Firstpage
934
Lastpage
939
Abstract
In software product line development, consistency among artifacts is important because commonalities and variabilities increase the complexity of relations among artifacts. For small scale models, the relations among elements can be easily identified and tracked by manually analyzing the descriptions of models. But when the complexity of models is high, a more systematic approach is required for identifying traceability information and verifying consistency between models. In this paper, by utilizing Formal Concept Analysis (FCA) and Prototype Verification System (PVS), we present a formal approach for identifying traceability and verifying consistency between feature model and component and connector view of software architecture.
Keywords
formal verification; software architecture; formal approach; formal concept analysis; mapping relation verification; prototype verification system; small scale models; software architecture; software product line development; traceability information; Asset management; Computer architecture; Connectors; Formal verification; Information technology; Prototypes; Software architecture; Software development management; Software prototyping; Watches;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer and Information Technology, 2007. CIT 2007. 7th IEEE International Conference on
Conference_Location
Aizu-Wakamatsu, Fukushima
Print_ISBN
978-0-7695-2983-7
Type
conf
DOI
10.1109/CIT.2007.111
Filename
4385205
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