Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method

Author

Chandorkar, A.N. ; Mande, Sudhakar ; Iwai, Hiroshi

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

215

Lastpage

218

Abstract

This paper studies various double-gate (DG) FinFET structures optimized for better Â¿off stateÂ¿ and Â¿on stateÂ¿ performance. In this work, we study the impact of process variation on the performance of DG-FinFET device with 20 nm gate length. This was achieved through calibrated TCAD simulations. We show that the spacer thickness variation has the highest impact on I_on of the DG-FinFETs. In this work, we also have demonstrated the suitability of method of Plackett-Burman design of experiments (PB-DOE), for accurate estimation of the impact of the large number of process parameter-variations on DG-FinFET deviceÂ¿s electrical performance.

Keywords

CMOS integrated circuits; design of experiments; integrated circuit design; power MOSFET; DG-FinFET device; Plackett-Burman design; TCAD simulations; design of experiment method; double-gate FinFET structures; process variation estimation; size 20 nm; CMOS technology; Circuit optimization; Design engineering; Design methodology; FinFETs; Fluctuations; Integrated circuit technology; MOSFETs; State estimation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734510

Filename

4734510