Title :
Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking
Author :
Kim, Bioh ; Sharbono, Charles ; Ritzdorf, Tom ; Schmauch, Dan
Author_Institution :
Semitool, Inc., Kalispell, MT
Abstract :
Through-silicon-via (TSV) copper electrodes can provide shortest-length and highest-density connections with reduced signal delay and power consumption. The issues involved with making TSV processes manufacturable include: (a) via shape and angle control; (b) insulator, barrier, and seed deposition with good conformality and adhesion; (c) void-free via filling with copper; (d) metal removal by CMP; (e) wafer thinning with small total-thickness-variation and with no critical defects; (f) via rerouting in the case of stacking heterogeneous chips; and (g) cost-effective wafer bonding. Copper deposition within high aspect ratio vias is one of the key technologies. We investigated the impacts of varying deposition conditions on the copper filling within a high aspect ratio via (AR > 8). We found that reducing current crowding at the via mouth and mass transfer limitations at the via bottom by optimizing deposition conditions is critical in achieving void-free, bottom-up filling. Bath composition and waveform have a significant influence on the filling profile at a fixed average current density. This study found that the plating bath requires a high metal concentration and a strong super-conformal capability. For a wide range of bath compositions (i. e., inorganic and organic concentrations), pulse reverse waveforms with the proper waveform parameters are required for reducing overhang and assisting bottom-up filling within a high aspect ratio via. With increasing average current density and all other process variables fixed, deposit profiles change significantly, which leads to higher tendency of overhang at the via mouth. This is attributed to current crowding at the via mouth and mass-transfer limitations at the via bottom. With optimized deposition conditions, we demonstrated void-free, bottom-up filling with a variety of via dimensions. Currently we are working on achieving higher filling rates. Initial tests with a modified bath composition showed that we may ac- - hieve at least two times faster filling rate with direct current
Keywords :
chemical mechanical polishing; chip scale packaging; current density; electrodes; wafer bonding; 3D chip stacking; angle control; aspect ratio; chemical mechanical polishing; copper deposition; copper electrodes; copper filling process; current crowding; current density; deep vias; filling profile; metal removal; pulse reverse waveforms; through-silicon-via; via rerouting; via shape; void-free via filling; wafer bonding; wafer thinning; Copper; Current density; Delay; Electrodes; Filling; Mouth; Proximity effect; Shape control; Stacking; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location :
San Diego, CA
Print_ISBN :
1-4244-0152-6
DOI :
10.1109/ECTC.2006.1645755