Misalignment issue between the si-body and the gate of a 30nm bSPIFET

Author

Tseng, Hung-Jen ; Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Jheng, Bao-Tang ; Tseng, Yi-Ming ; Kang, Shiang-Shi ; Tasi, Ying-Chieh

Author_Institution

Dep. of Electr. Eng., Nat. Sun Yat-Sen Univ. (NSYSU EE), Kaohsiung, Taiwan

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

227

Lastpage

230

Abstract

To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability of the device.

Keywords

CMOS integrated circuits; elemental semiconductors; field effect transistors; semiconductor device models; semiconductor device reliability; silicon; 2D simulation; Si; bSPIFET; block-oxide field-effect transistor; device stability; gate shift misalignment; reliability; self-aligned process; short channel degradation; size 30 nm; Chemical vapor deposition; Contact resistance; Degradation; Dry etching; FETs; Fabrication; FinFETs; High K dielectric materials; High-K gate dielectrics; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734513

Filename

4734513