A low power charge-redistribution ADC with reduced capacitor array

This paper presents a novel design of low power charge redistribution successive approximation analog to digital converter (CR-SAR ADC). During its conversion, the voltage swing of the capacitor array is reduced to half of the voltage reference without decreasing the ADC dynamic range. The reduced voltage swing results in a significant reduction of ADC power consumption. Also, the proposed design requires only half of the total capacitance that is used in a traditional CR-SAR ADC with the same resolution. MATLAB simulations are performed to compare the power consumption due to charging the capacitor array in the proposed and previous low power CR-SAR ADC´S. The proposed circuit is implemented using a 0.13¿ CMOS technology. Post-layout simulation shows that the proposed converter consumes 63% less energy compared to a traditional CR-SAR ADC.