Title :
Plasma-process induced damage on 65nm logic VLSI manufacturing
Author :
Pan, Jing ; Wu, Jimmy ; Gan, Howard ; Qi Wang ; Bei, Emily ; Wang, Qi ; Nie, Jiaxiang ; Liao, Chin Chang ; Ning, Jay
Author_Institution :
Logic Technol. Dev., Semicond. Manuf. Int. Corp., Beijing, China
Abstract :
Plasma-process induced damage (P2ID) is a serious yield and reliability concern with the continuous VLSI technical node shrinkage. In this paper, P2ID on 65 nm node VLSI manufacturing development is investigated. Plasma in high-density plasma deposition (HDP), preclean of physical vapor deposition (PVD) and reactive ion etching (RIE) processes have significant negative impact on P2ID. Respective improving actions have been implemented then on following processes: pre-metal dielectric (PMD) deposition, pre-clean before Cu barrier deposition and passivation etching for Al pad. As a result, P2ID free process has been achieved for logic 65 nm processes.
Keywords :
VLSI; integrated circuit reliability; integrated circuit yield; sputter etching; barrier deposition; high-density plasma deposition; integrated circuit reliability; integrated circuit yield; logic VLSI manufacturing; passivation etching; physical vapor deposition; plasma-process induced damage; reactive ion etching; size 65 nm; technical node shrinkage; Atherosclerosis; Chemical vapor deposition; Dielectrics; Etching; Logic; Passivation; Plasma applications; Plasma materials processing; Pulp manufacturing; Very large scale integration;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734519
