DocumentCode :
2143005
Title :
Orchestrator: A low-cost solution to reduce voltage emergencies for multi-threaded applications
Author :
Hu, Xing ; Yan, Guihai ; Hu, Yu ; Li, Xiaowei
Author_Institution :
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
fYear :
2013
fDate :
18-22 March 2013
Firstpage :
208
Lastpage :
213
Abstract :
Voltage emergencies have become a major challenge to multi-core processors because core-to-core resonance may put all cores into danger which jeopardizes system reliability. We observed that the applications following SPMD (Single Program and Multiple Data) programming model tend to spark domain-wide voltage resonance because multiple threads sharing the same function body exhibit similar power activity. When threads are judiciously relocated among the cores, the voltage droops can be greatly reduced. We propose “Orchestrator”, a sensor-free non-intrusive scheme for multi-core architectures to smooth the voltage droops. Orchestrator focuses on the inter-core voltage interactions, and maximally leverages the thread diversity to avoid voltage droops synergy among cores. Experimental results show that Orchestrator can reduce up to 64% voltage emergencies on average, meanwhile improving performance.
Keywords :
Accuracy; Benchmark testing; Instruction sets; Monitoring; Multicore processing; Regression tree analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference_Location :
Grenoble, France
ISSN :
1530-1591
Print_ISBN :
978-1-4673-5071-6
Type :
conf
DOI :
10.7873/DATE.2013.056
Filename :
6513502
Link To Document :
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