Title :
Systematic evaluation of die thinning application in a power SIPs by simulation
Author :
Liu, Yong ; Desbiens, Don ; Irving, Scott ; Luk, Timwah ; Lolar, Carl ; Liu, Yumin ; Qian, Qiuxiao
Author_Institution :
Fairchild Semicond., South Portland, ME
Abstract :
In this paper, a lead frame based system in package (SIP) for power management is examined. This package is built using multiple die types including power IGBTs, diodes, and IC controllers. To maximize product performance the power components use an ultra thin back grind. Thin dies minimize RDS(on), maximize thermal performance, and minimize the board standoff height by allowing the package to be thinner. However, the ultra thin die could be a potential risk for die cracking if it is done without careful evaluation, especially for die thickness as thin as 90 mum and 50 mum. So it is critical to understand the impact of thinning dies on the reliability of the product in assembly manufacture and vary reliability tests. Modeling and simulation with a smaller amount of empirical testing is a good way to evaluate this thin die application quickly and at a lower cost. Therefore, the objective of this paper is to fully investigate the thin die application in a power SIP with systematic simulation and analysis before real application. A large complicated and advanced 3D FEA model framework is developed for the SIP. The major modeling and evaluation work is categorized into two areas: One is to check the impact of the thin die on different assembly processes. The other is to simulate the major reliability tests such as temperature cycle (TMCL) and component-level reflow process. Comprehensive evaluation and analysis of the modeling and simulation results for the thin die application to a Fairchild power SIP are presented
Keywords :
assembling; finite element analysis; integrated circuit reliability; system-in-package; 3D FEA model; assembly manufacture; assembly processes; component-level reflow process; die cracking; die thinning; finite element analysis; lead frame packaging; power SIP; reliability tests; system in package; temperature cycle test; ultra thin die; Analytical models; Assembly; Diodes; Energy management; Insulated gate bipolar transistors; Integrated circuit packaging; Power system management; Power system modeling; Semiconductor device modeling; Testing;
Conference_Titel :
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location :
San Diego, CA
Print_ISBN :
1-4244-0152-6
DOI :
10.1109/ECTC.2006.1645773