Designing for 1/sup st/ and 2/sup nd/ level reliability of micro-electronic packages using combined experimental - numerical techniques

Author

van Silfhout, R.B.R. ; Jansen, M.Y. ; van Driel, W.D. ; Zhang, G.Q.

Author_Institution

Philips Appl. Technol., Eindhoven

fYear

0

fDate

0-0 0

Abstract

This paper presents our effort to predict IC, packaging, and board level reliability problems. Micro-electronic based reliability problems are driven by the mismatch between the different material properties, such as thermal expansion, hygro-swelling, and/or the degradation of interfacial strength. In the past, such reliability problems were treated separately, but recent development have made clear that total product reliability concerns the interaction of IC, package, and PCB. This paper presents parts of our strategy to assess this integrated reliability by combining experimental and numerical techniques

Keywords

failure analysis; integrated circuit packaging; integrated circuit reliability; board level reliability; integrated circuit reliability; interfacial strength; material properties; microelectronic packages; packaging reliability; product reliability; reliability problems; Delamination; Electronic packaging thermal management; Electronics industry; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit testing; Predictive models; Solid modeling; Temperature; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2006. Proceedings. 56th

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

1-4244-0152-6

Type

conf

DOI

10.1109/ECTC.2006.1645774

Filename

1645774