DocumentCode :
2143368
Title :
Rheological characterization and full 3D mold flow simulation in multi-die stack CSP of chip array packaging
Author :
Lee, Min Woo ; Khim, Jin Young ; Yoo, Min ; Chung, JiYoung ; Lee, Choon Heung
Author_Institution :
Amkor Technol. Korea, Seoul
fYear :
0
fDate :
0-0 0
Abstract :
According as high density packaging options such as 2 or more die stacking or package stacking technologies are developed, the major mold process related quality concerns such as incomplete mold, exposed wires and wire sweeping are increased because of their narrow spaces between die top and mold surface and increased wiring density. So, to verify those concerns, full 3D rheokinetic simulation of mold flow has been investigated for 3 die stacking structure of 4 times 4 mold array, 294LD case. The rheological parameters of commercial epoxy molding compound (EMC) were acquired through the slit-die rheometer and DSC (differential scanning calorie-meter) analysis. It is found that the severe void problem is one of the challenging factors in the thin and multi-die stack packaging to determine its manufacturability. To investigate the effect of different gate types, the molding options with four different gates were evaluated. The center gate showed most severe voids but corner gate showed relatively better void performance. But in case of the wire sweeping experiment and prediction results, the center gate type had less wire sweeping than the corner gate type. In the rheological simulation results, the corner gate case indicated increased velocity, shear stress and mold pressure near to the gate inlet and final filling zone. The experimental case study and the mold filling simulation showed good match on the mold external void and wire sweeping related prediction
Keywords :
chip scale packaging; flow simulation; moulding; semiconductor process modelling; voids (solid); 3D mold flow simulation; 3D rheokinetic simulation; chip array packaging; chip scale packaging; differential scanning calorimeter; epoxy molding compound; mold filling simulation; mold process; multidie stack packaging; package stacking; rheological characterization; slit-die rheometer; void problem; wire sweeping; Chip scale packaging; Electromagnetic compatibility; Filling; Manufacturing; Rheology; Space technology; Stacking; Stress; Wire; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location :
San Diego, CA
ISSN :
0569-5503
Print_ISBN :
1-4244-0152-6
Type :
conf
DOI :
10.1109/ECTC.2006.1645780
Filename :
1645780
Link To Document :
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