Title :
CDM ESD failure modes and VFTLP testing for protection evaluation
Author :
Zhou, Yuanzhong Paul ; Hajjar, Jean-Jacques
Author_Institution :
Analog Devices, Wilmington, MA, USA
Abstract :
Most integrated circuit ESD damages are caused by CDM stresses. This paper discusses CDM failure modes. The most common such failure is damage to the gate oxide in the MOS device. A new methodology that uses a gate oxide damage monitor and modified VFTLP testing is proposed for assessing CDM protection effectiveness and robustness in I/O circuits. A test structure for such an evaluation is also introduced.
Keywords :
MOS integrated circuits; electrostatic discharge; integrated circuit reliability; integrated circuit testing; radiation hardening (electronics); CDM ESD failure modes; CDM failure mode; MOS device; VFTLP testing; charge device model; gate oxide damage monitor; human body model; integrated circuit ESD damages; protection evaluation; transmission line pulse; Biological system modeling; Circuit testing; Condition monitoring; Electrostatic discharge; MOS devices; Power supplies; Protection; Robustness; Stress; Voltage;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734539
