Multi-transputer video coding (MTVC) system

Author

Chong, M.N.

Author_Institution

Sch. of Electr. Eng., Nanyang Technol. Univ., Singapore

Volume

3

fYear

1993

fDate

19-21 Oct. 1993

Firstpage

394

Abstract

A novel approach for the parallel implementation of a CCITT H.261 video coding algorithm on a multiprocessor network is presented. One of the prominent bottlenecks of parallel implementation of a video coding algorithm is the sequential operation of the bit rate control in the coding algorithm. An a priori buffer-fullness estimator is proposed to circumvent this sequential operation which involves changing the quantisation step-size at fixed intervals.<>

Keywords

analogue-digital conversion; buffer storage; discrete cosine transforms; image coding; parallel architectures; parameter estimation; transputer systems; video signals; CCITT H.261 video coding algorithm; MTVC system; a priori buffer-fullness estimator; bit rate control; multiprocessor network; multitransputer video coding system; parallel implementation; quantisation step-size; sequential operation; Bit rate; Costs; Discrete cosine transforms; Educational institutions; Image coding; Motion estimation; Network topology; Partitioning algorithms; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on

Conference_Location

Beijing, China

Print_ISBN

0-7803-1233-3

Type

conf

DOI

10.1109/TENCON.1993.328006

Filename

328006