Title :
Structural fault collapsing by superposition of BDDs for test generation in digital circuits
Author :
Ubar, R. ; Mironov, D. ; Raik, J. ; Jutman, A.
Author_Institution :
Dept. of Comput. Eng., TTU, Tallinn, Estonia
Abstract :
The paper presents a new structural fault-independent fault collapsing method based on the topology analysis of the circuit, which has linear complexity. The minimal necessary set of faults as the target objective for test generation is found. The main idea is to produce fault collapsing concurrently with the construction of structurally synthesized binary decision diagrams (SSBDD) used for test generation, as a side effect. To improve the fault collapsing, a new class of BDDs in a form of SSBDDs with multiple inputs (SSMIBDD) is proposed, which allows a significant reduction of the model complexity for test generation purposes, and produces collapsed fault sets with less sizes than the SSBDDs provide. Experimental data show that the fault collapsing by the proposed method is considerably more efficient than other structural fault collapsing methods with comparative time cost. The method is especially efficient for circuits with high rate of internal fanouts.
Keywords :
binary decision diagrams; circuit testing; digital circuits; fault diagnosis; network synthesis; circuit topology; digital circuit test generation; model complexity; structural fault-independent fault collapsing method; structurally synthesized binary decision diagrams; Automatic test pattern generation; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Circuit topology; Data structures; Digital circuits; Fault detection; Fault diagnosis; Digital circuits; SSBDDs with multiple inputs; Structurally Synthesized BDDs; fault collapsing; fault equivalence and dominance; test generation;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450451