DocumentCode :
2143857
Title :
Future of GPGPU micro-architectural parameters
Author :
Nugteren, Cedric ; van den Braak, Gert-Jan ; Corporaal, Henk
Author_Institution :
Eindhoven University of Technology, The Netherlands
fYear :
2013
fDate :
18-22 March 2013
Firstpage :
392
Lastpage :
395
Abstract :
As graphics processing units (GPUs) are becoming increasingly popular for general purpose workloads (GPGPU), the question arises how such processors will evolve architecturally in the near future. In this work, we identify and discuss trade-offs for three GPU architecture parameters: active thread count, compute-memory ratio, and cluster and warp sizing. For each parameter, we propose changes to improve GPU design, keeping in mind trends such as dark silicon and the increasing popularity of GPGPU architectures. A key-enabler is dynamism and workload-adaptiveness, enabling among others: dynamic register file sizing, latency aware scheduling, roofline-aware DVFS, run-time cluster fusion, and dynamic warp sizing.
Keywords :
Clocks; Computer architecture; Dynamic scheduling; Graphics processing units; Instruction sets; Pipelines; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference_Location :
Grenoble, France
ISSN :
1530-1591
Print_ISBN :
978-1-4673-5071-6
Type :
conf
DOI :
10.7873/DATE.2013.089
Filename :
6513535
Link To Document :
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