A New Efficient Replacement Policy for Scratch Pad Memory

With the implausible rise in microprocessor technology having high speed processors and enhanced the processor-memory speed gap, the design of on chip memory hierarchy is a momentous concern in embedded systems. This paper describes a simulation based performance evaluation of typical cache vs. scratch-pad memory (SPM) design issues in embedded systems such as associativity and replacement policies. The evaluation in paper is done using Simple Scalar simulation tools. in addition, we propose the use of new cache replacement policy, called tag based dual cache replacement policy in SPM and access the best approach for replacement in SPM for embedded systems. According to our simulation results, proposed replacement approach in SPM effectively decreases the data miss ratio of the cache. Comparisons against a SPM solution using dual replacement policy show remarkable advantage of up to 20% in cache miss rate for designs of the same memory size.