Comparative analysis and study of metastability on high-performance flip-flops

In this paper, we analyze and characterize the metastability of 11 previously proposed high-performance flip-flops, reduced clock-swing flip-flops, and level-converting flip-flops. From extensive simulation results in 65nm CMOS technology, the main metastability parameters of ¿ and T₀ are extracted and analyzed at both nominal and reduced supply voltage. Our simulation results indicate that these flip-flops exhibit a wide range (up to few orders of magnitudes) of metastability windows. In particular, flip-flops with differential and positive feedback configuration such as the sense-amplifier based flip-flops demonstrate the most optimal metastability. Based on this finding, a novel pre-discharge flip-flop (PDFF) with positive feedback configuration is proposed. Extensive simulation results reveal that PDFF achieves better metastability than the previous proposed flip-flops at both nominal voltage supply and nominal voltage supply with reduced clock-swing.