Title :
Wafer-scale processing of aligned carbon nanotubes for future integrated circuits
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
We demonstrated essential technological components for wafer-scale integrated CMOS nanotube circuits such as inverters, NAND, and NOR logic gates: 1.The full-wafer-scale synthesis and transfer of massively aligned carbon nanotubes, and device fabrication on 4 inch substrates 2. In-depth device study and tuning, and extensive doping study for the first wafer-scale integrated CMOS nanotube circuits. 3. A novel device structure such as defect-tolerate logic gate.
Keywords :
CMOS integrated circuits; carbon nanotubes; circuit tuning; logic circuits; logic gates; nanotube devices; wafer-scale integration; C; NAND logic gates; NOR logic gates; defect-tolerate logic gate; extensive doping; integrated circuits; inverters; massively aligned carbon nanotubes; size 4 inch; tuning; wafer-scale integrated CMOS nanotube circuits; wafer-scale processing; CMOS logic circuits; CMOS technology; Carbon nanotubes; Fabrication; Integrated circuit synthesis; Integrated circuit technology; Logic devices; Logic gates; Nanoscale devices; Pulse inverters;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734597
