• DocumentCode
    2144845
  • Title

    Investigations on delay interconnect lines for high-speed designs with the numerical technique

  • Author

    Yuan, Weiliang ; Li, Er-Ping

  • Author_Institution
    CEE Div., Inst. of High Performance Comput., Science Park II, Singapore
  • Volume
    2
  • fYear
    2003
  • fDate
    18-22 Aug. 2003
  • Firstpage
    575
  • Abstract
    With the advancements in electronics, interests in interconnect and package in high-speed circuits are greatly increased. For precise timing among high-speed modules to synchronize signals and harmonize communication between modules, interconnect need be designed with high accuracy and are often meandered to equalize delay. The paper will present the investigations on the effects of different serpentine interconnect lines with various spacing, thickness and rise/fall edges on delay with a full-wave numerical technique, the finite-difference time-domain method. The insights and results acquired can be used to verify and optimize interconnect and timing designs for signal integrity purposes.
  • Keywords
    finite difference time-domain analysis; high-speed integrated circuits; integrated circuit interconnections; delay interconnect lines; finite-difference time-domain method; high-speed circuits; high-speed modules; numerical technique; serpentine; signal integrity; timing designs; Analytical models; Clocks; Delay effects; Delay lines; Design optimization; Finite difference methods; Integrated circuit interconnections; Signal design; Time domain analysis; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electromagnetic Compatibility, 2003 IEEE International Symposium on
  • Print_ISBN
    0-7803-7835-0
  • Type

    conf

  • DOI
    10.1109/ISEMC.2003.1236666
  • Filename
    1236666