DocumentCode :
2144854
Title :
Clock buffer polarity assignment considering capacitive load
Author :
Lu, Jianchao ; Taskin, Baris
Author_Institution :
Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USA
fYear :
2010
fDate :
22-24 March 2010
Firstpage :
765
Lastpage :
770
Abstract :
A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.
Keywords :
buffer circuits; capacitance; circuit optimisation; clocks; dynamic programming; integrated circuit design; capacitive load; clock buffer polarity assignment; clock tree; driving capacitance; peak current; pseudo polynomial dynamic programming; Capacitance; Circuit noise; Clocks; Current supplies; Dynamic programming; Inverters; Noise reduction; Power supplies; Rails; Switches; Clock network; polarity assignment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
ISSN :
1948-3287
Print_ISBN :
978-1-4244-6454-8
Type :
conf
DOI :
10.1109/ISQED.2010.5450493
Filename :
5450493
Link To Document :
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