Author :
Matsuura, Yoshihiro ; Watanabe, Akio ; Kawakami, Satoko
Abstract :
This paper presents the stacked die SiP technology suitable for the devices with low-k inter-layer dielectric "low-k ILD". As devices with low-k ILD increase in number, they have also come to be used in stacked die SiP. The low-k ILD material is however, known to have a fragile characteristic. Combined with the stacked die SiP which has a limitation in die size and height for use in cellular phones and the like, it is very important to care about the influence on the device with low-k ILD because package structure is complex and the die thickness needs to be thin. To develop this type of stacked die SiP, we investigated and focused on two subjects. One was, how to control the thermal and mechanical stress on the die in the assembly. The other was, how eliminate cracks in the low-k ILD. On the first subject, the suitable package structure was examined to minimize the stress on the device with low-k ILD, and the result was that the structure of the device with low-k ILD placed the top of the stacked dies is the best. However, this has an overhang on the device with low-k ILD. There is therefore a risk of damaging the device with low-k ILD as the die is stressed during the wire bonding process. We therefore examined wire bonding conditions with simulation of stress by the bonding load on the die in advance, and from there, established the suitable wire bonding process. On the second subject, the dicing process exposes the die to the generation of crack initiation points. After the evaluation, the new dicing process with the laser groove dicing was effective in controlling possibilities of crack occurrence in devices experiencing large stress. Thus, this new process is applied to the product depending on a package structure, a package type, and so on. Finally, samples of real products in mass production were put through reliability tests and they passed. Stacked die SiP for thin devices with low-k ILD technology has therefore been established
Keywords :
lead bonding; low-k dielectric thin films; silicon compounds; stress effects; system-in-package; thermal stress cracking; cellular phones; crack initiation points; dicing process; die assembly; low-k ILD; low-k interlayer dielectric devices; mechanical stress control; stacked die SiP technology; thermal stress control; wire bonding conditions; Assembly; Biological materials; Bonding processes; Cellular phones; Dielectric devices; Dielectric materials; Packaging; Stress control; Thermal stresses; Wire;
