Comprehensive study of bias temperature instability on polycrystalline silicon thin-film transistors

Author

Huang, C.-F. ; Chen, Y.-T. ; Sun, H.-C. ; Liu, C.W. ; Hsu, Y.-C. ; Shih, C.-C. ; Lin, K.-C. ; Chen, J.-S.

Author_Institution

Dept. of Electr. Eng. & Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

624

Lastpage

627

Abstract

The negative and positive bias temperature instabilities are investigated on p-channel and n-channel TFTs with four different combinations. The stress-induced hump in the subthreshold region is observed for PBTI on p-channel TFTs and NBTI on n-channel TFTs. The hump is attributed to the edge transistors along the channel width direction. Higher electric field at the corners induces more trapped carriers in the insulator as compared to channel transistor. In contrast, no humps are observed for NBTI on p-channel TFTs and PBTI on n-channel TFTs. For NBTI on p-channel TFTs, the interface traps are generated by breaking the Si-H bonds and are responsible for the negative Â¿V_T. On the other hand, electrons are trapped in the insulator and induce positive Â¿V_T for PBTI on n-channel TFTs.

Keywords

radiation hardening (electronics); semiconductor device models; semiconductor device reliability; thin film transistors; bias temperature instability; channel transistor; channel width direction; polycrystalline silicon thin-film transistors; Electron traps; Insulation; MOSFETs; Niobium compounds; Plasma temperature; Silicon; Stress; Thin film transistors; Threshold voltage; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734622

Filename

4734622