Title :
Yield improvement of 3D ICs in the presence of defects in through signal vias
Author :
Nain, Rajeev K. ; Pinge, Shantesh ; Chrzanowska-Jeske, Malgorzata
Author_Institution :
Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
Abstract :
Through signal vias (TSVs) in 3D ICs suffer from thermo-mechanical stress, and may fail or attain plasticity resulting in significant yield loss. We present a novel set of strategies for yield improvement in the presence of defects in through signal vias in heterogeneous 3D system-on-chip. Monte-Carlo simulation results show that our strategy can improve the yield of 3D ICs significantly. Furthermore, we estimate the parametric yield and present a quantitative analysis of the impact of our approach on chip area, power, performance and chip revenue that can improve profitability. Our results suggest that the proposed strategies can be very useful in yield-aware 3D design.
Keywords :
Monte Carlo methods; failure analysis; integrated circuit yield; system-on-chip; three-dimensional integrated circuits; 3D IC; Monte-Carlo simulation; chip area; circuit defect; heterogeneous 3D system-on-chip; parametric yield; plasticity; profitability; thermo-mechanical stress; through signal vias; yield improvement; yield loss; Costs; Integrated circuit interconnections; Memory architecture; Stacking; System-on-a-chip; Thermal stresses; Thermomechanical processes; Through-silicon vias; Throughput; Yield estimation;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450513
