DocumentCode
2145738
Title
Energy-efficient multicore chip design through cross-layer approach
Author
Wettin, Paul ; Murray, Jacob ; Pande, Partha ; Shirazi, Behrooz ; Ganguly, Amlan
Author_Institution
School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA
fYear
2013
fDate
18-22 March 2013
Firstpage
725
Lastpage
730
Abstract
Traditional multi-core designs, based on the Network-on-Chip (NoC) paradigm, suffer from high latency and power dissipation as the system size scales up due to the inherent multi-hop nature of communication. Introducing long-range, low power, and high-bandwidth, single-hop links between far apart cores can significantly enhance the performance of NoC fabrics. In this paper, we propose design of a small-world network based NoC architecture with on-chip millimeter (mm)-wave wireless links. The millimeter wave small-world NoC (mSWNoC) is capable of improving the overall latency and energy dissipation characteristics compared to the conventional mesh-based counterpart. The mSWNoC helps in improving the energy dissipation, and hence the thermal profile, even further in presence of network-level dynamic voltage and frequency scaling (DVFS) without incurring any additional latency penalty.
Keywords
Bandwidth; Benchmark testing; Energy dissipation; Multicore processing; Switches; Voltage control; Wireless communication; DVFS; NoC; mm-wave; small world; wireless;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference_Location
Grenoble, France
ISSN
1530-1591
Print_ISBN
978-1-4673-5071-6
Type
conf
DOI
10.7873/DATE.2013.156
Filename
6513602
Link To Document