Copper die bumps (first level interconnect) and low-K dielectrics in 65nm high volume manufacturing

The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD´s) into back end interconnect architectures have made integrating copper bumps challenging, i.e. low-k ILD cracking that often leads to partial or complete die failure. For the 65nm technology node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead (SnPb) package-side bumps in high volume manufacturing (HVM). Advantages of using copper die bumps include lowering the bump critical dimension (CD) floor, continued downward scaling of passivation opening size, a drastically simplified underbump metallization (UBM) scheme that projects to improved electromigration resistance, and extensions to higher 10 densities. This paper will discuss some of these gains