Efficient realization for a class of clock-controlled sequence generators

In this article, the hardware implementation of a 2-2 sequence generator is discussed. A novel architecture for the 1-2 generator using an extended linear feedback shift register (XLFSR) is presented. Compared to the conventional LFSR based schemes, the proposed scheme is advantageous in the sense that it yields generators of high and constant throughput. When this scheme is used to implement generators in VLSI technologies, low area and power consumption are also expected. Moreover, it has been shown that the proposed 1-2 generators are very suitable for building long Gollmann´s cascaded generators