Title :
Methodology to ensure circuit robustness and exceptional silicon quality while proliferating designs across process revisions with high productivity
Author_Institution :
Integrated Syst. (intsys), India
Abstract :
This paper describes methodologies developed to ensure circuit robustness and silicon quality when a high performance microprocessor design is proliferated across process revisions. The paper describes innovative techniques and solutions based on data obtained from post silicon experiments and simulations that can be advantageous to the designers. The paper focuses on the areas of leakage control, noise tolerance, min-delay analysis.
Keywords :
logic design; microprocessor chips; silicon; circuit robustness; high performance microprocessor design; leakage control; min-delay analysis; noise tolerance; silicon quality; Circuit noise; Circuit simulation; Failure analysis; Logic design; Microprocessors; Process design; Productivity; Robustness; Silicon; Timing; Silicon quality; design methodology; design proliferation; leakage; min-delay; noise; performance verification; process revision;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450532