Electrical-optical high speed serial server scalability link

Increased demand for performance continues to drive higher chip internal clock frequencies and parallelism, as well as raise the demand for higher bandwidth and lower latencies. Today´s copper digital communication links are limited by their loss characteristic which are dominated at high data rates by skin effects and dielectric loss (Broomall, 1997). Electrical copper links are typically used to interconnect multiple processor subsystems to build symmetric multi-processor (SMP) systems, as well as to connect input/output (I/O) subsystems across relative long distances. This paper describes the electrical design, challenges, and validation encountered during the design of a highly scalable, modular SMP server (Brown, 2002) with data rates of 3.2 GT/s (gigatransfers per second) and higher. It contrasts the all-copper external cable and copper-to-optical interconnect technology to achieve the overall system design goals from the perspective of link performance, electrical challenges, and physical design constraints. Key design parameters such as AC coupling capacitor selection and layout optimization, via stub and antipad effects, and raw card materials are discussed in this paper