Constraint analysis and debugging for multi-million instance SoC designs

Timing constraints are used by implementation tools in all design stages in modern design flows. With the growing complexity of designs and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems. In this paper, we present the technology of an interactive constraint debugger that automatically checks constraint problems, and provides context-sensitive diagnosis and fix suggestions. Our extensive user feedback shows that the tool significantly improves designer productivity.