Title :
Variation aware guard -banding for SOC static timing analysis
Author :
Wong, Vee Kin ; Teng, Siong Kiong
Author_Institution :
Intel Microelectron. (M) Sdn. Bhd. Penang, Malaysia
Abstract :
The conventional approach to static timing analysis (STA) is to apply a constant guard-band against parameter variation. This can lead to costly and inefficient design. In this paper, we show that the guard-band can be reduced through statistical methods applied using an industry standard STA tool while preserving pessimism to ensure design quality and yield.
Keywords :
electronic engineering computing; integrated circuit design; program diagnostics; statistical analysis; system-on-chip; SOC static timing analysis; STA; constant guard-band; design quality; parameter variation; statistical methods; variation aware guard-banding; Clocks; Delay; Electronic design automation and methodology; Logic design; Microelectronics; Performance analysis; Random number generation; Sampling methods; Statistical analysis; Timing; Static timing analysis; performance verification; variation;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450541
